Transistor Trick Beats Moore
EE Times, 9/14/2016 00:01 AM EDT
LAKE WALES, Fla. — Researchers at Zvi OrBach's startup Zeno Semiconductor (Sunnyvale, Calif.) are claiming a power-boosting breakthrough for use at any semiconductor node to increase drive by 2X and power-delay by 4X, compared with the average 30 percent improvement when advancing to the next Moore's node.
Their process is but one example of the future of semiconductors, now that the International Technology Roadmap for Semiconductors (ITRS 2015) has declared 10-nanometer the last "Moore's Law" node, with future chip progress depending on More than Moore innovations such as 3-D, new channel materials and novel architectures like Zeno Semi's.
Disclosed today at the European Solid State Device Research Conference (ESSDRC 2016, Lausanne, Switzerland) the boosted transistor paper was a collaborative effort among Zeno Semi, Synopsys, and Stanford University, titled A CMOS-Compatible Boosted Transistor Having >2x Drive Current and Low Leakage Current. It follows the one-transistor SRAM presented by Zeno last year.
Zvi Or-Bach is an investor and executive chairman at Zeno Semiconductor, as well as a frequent contributor to EE Times, but the idea behind Zeno's breakthrough technology came from the principle author of the ESSDRC paper, namely Jin-Woo Han.
Called βMOS by its inventor, the buried n-well is the trick that isolates the p-well channel to boost its current carrying capabilities by 2X and its power-delay by 4X, shown at left with a transmission electron microscope (TEM). (Source: Zeno)
"Jin-Woo Han was picked for one of Obama's young scientists awards while at NASA," Or-Bach told EE Times.
Han's 2016 award was for nanodevices and nano-electronics at the Universities Space Research Association of Washington, based at NASA's Ames Research Center (Moffett Field, Calif.)
Basically Han discovered how to have-your-cake-and-eat-it-too by inventing a transistor architecture that could operate as either a low-power metal oxide semiconductor field-effect transistor (MOSFET) or could instantly switch to a high-power bipolar-junction transistor (BJT).
"Han's transistor operates in two modes, one in low bias for low power by reducing its operating voltage, and the other a high-power mode with a higher bias voltage for better speed and higher power driving capabilities," OrBach told EE Times.
Zeno Semi owns the dual-mode transistor intellectual property (IP), which it intends to license to all comers. Called βMOS, it allows users stay at their current low-cost scaling node (or even drop back a node or two for die savings). All the while reaping even more benefits than are achieved by using the advanced nodes (which come at a premium price due to lower yields and the ballooning prices of fab equipment).
The Han βMOS transistor operates between 0.6-and-1.0 volts, with good performance and low power at the lower voltage setting which grows exponentially (squared) as it approaches 1-volt where it achieves twice the drive and four times the power-delay factor.
Zeno Semi employees and investors are not the only ones endorsing the new "More than Moore" technology that promises to roll back the price/performance gained by scaling. In particular, professor Masaharu Kobayashi at the University of Tokyo, a specialist in steep sub-threshold devices, says the Zeno-transistor breakthrough is genuine and of great value.
"Energy efficiency is the most important metric for current high performance and low power computing in an energy-aware global society. In general, high energy efficiency can be achieved by increasing transistor’s on/off current ratio. There are tremendous amount of work ongoing to improve this parameter by using steep sub-threshold-slope transistors. But most of the steep-slope transistor technologies are far from realistically manufacturable, because of their complicated process integration scheme and significant circuit-layout modifications, both of which increase manufacturing costs a lot," Kobayashi told EE Times in an exclusive interview. "The boosted transistor invented by Zeno Semiconductor is a very promising solution which can achieve both high energy efficiency and low cost manufacturing. They integrate lateral and vertical BJTs into conventional MOSFETs without increasing the device's footprint. And they realize a positive feedback mechanism to enhance overall drain current, but maintain off-current. Bipolar transistors have been away from mainstream logic applications for decades, but now it has surprisingly come back as current booster of MOSFETs."
Zeno Semi's βMOS boosted architecture also works with low-power FinFETs which can be instantly boosted to a high-power FinBJT. (Source: Zeno)
Zemo Semi's paper last year described a single-transistor (1T) static random access memory (SRAM) using the same architecture as βMOS, but with a different backside bias setting. Since then, Han has discovered how to create a boost version of his transistors that could be used wherever occasional extra drive current would be useful.
"Zeno Semiconductor invented 1T SRAM technology using, in principle, the same feedback mechanism, which also attracts semiconductor industry especially for embedded application. I believe Zeno Semiconductor will change the game in the field of energy efficient computing by cost competitiveness of the boosted transistor and 1T SRAM," Kobayashi told EE Times.
Geert Eneman, senior researcher in the Semiconductor Technology and Systems (STS) division of IMEC (Heverlee, Belgium) concurs that Han's βMOS transistor could revolutionize an industry running up against the Moore's Law brick-wall of single atom dimensions.
"Transistors that combine improved performance at low supply voltage with low off-state leakage are notably hard to manufacture, especially for nFETs. Zeno Semiconductor's experimental demonstration of this boosted MOS structure is very promising as it proves that this device provides a controllable way to achieve an excellent drive current with a steep turn-on. Moreover, its off-state leakage is similar to conventional FETs and the device comes with a similar layout footprint. The boosted MOS technique should be compatible with FinFETs, stress engineering and alternative channel materials, which makes it an interesting candidate for next technology nodes," Eneman told EE Times in an exclusive interview.
Zeno Semi previously thought of their process as a memory technology, but now believe that by varying backside voltage bias it can now serve multiple purposes, making it a shoe-in as a More-than-Moore alternative to further chip scaling beyond 10-nanometer.
Fully depleted silicon-on insulator (FD-SOI) is also a shoe-in as a More-that-Moore technology, offering many of the same advantages, but at the cost of the more expensive SOI wafers, whereas βMOS uses standard bulk silicon wafers.
— R. Colin Johnson, Advanced Technology Editor, EE Times