Novel 1-Transistor SRAM Technology 5x Smaller and Lower Power than Conventional SRAM Demonstrated at 28nm Process Technology Sunnyvale, CA, December 10, 2015 – Zeno Semiconductor today announced its novel 1-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology at the IEDM Conference. Zeno’s 1-transistor Bi-SRAM uses a single transistor as the memory bitcell and is therefore 5x smaller than conventional SRAMs which use 6-transistor bitcells (6T-SRAM). When impl

0.025 square microns on 28nm CMOS LAKE WALES, Fla.—The smallest static random access memory (SRAM) to date fits in the space of a single metal-oxide semiconductor (MOS) transistor, according to serial entrepreneur and regular EE Times blogger, Zvi Or-Bach, executive chairman of the newest memory maker in Silicon Valley, Zeno Semiconductor Inc. (Sunnyvale, Calif.). Zeno Semiconductor unveiled its wares at the International Electron Devices Meeting (IEDM) on December 9th. (more