December - 2018

1-Transistor SRAM Cell Scales to FinFET Technology Node

1-Transistor SRAM Cell Scales to FinFET Technology Node

Zeno’s 1-transistor Bi-SRAM uses a single transistor and is ~5x smaller than a conventional SRAM -- which use 6-transistor bitcells (6T-SRAM) -- at the same technology node. One way to look at a System-on-Chip (SoC) is the proportions of silicon area that are devoted to new logic, reused logic (from an earlier design), and embedded memory. According to Semico Research, in 1999, the area devoted to memory averaged out at 17%. By 2018, embedded memory has become pervasive -- d

Zeno Demonstrates Scalability of World’s Smallest SRAM Bitcell Technology to FinFET Technology Node

1- /2-Transistor SRAM Technology Demonstrated at Standard FinFET Process Technology Sunnyvale, CA, December 5, 2018 – Zeno Semiconductor, a Silicon Catalyst Portfolio Company, demonstrated the scalability of its novel 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to FinFET technology node at the IEDM Conference. The results from 14nm and 16nm FinFET technology nodes from multiple foundries follow previous implementation of Bi-SRAM technol

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Zeno Demonstrates Scalability of World’s Smallest SRAM Bitcell Technology to FinFET Technology Node

A Boosted MOS Transistor

A Boosted MOS Transistor

Transistor Trick Beats Moore

Transistor Trick Beats Moore

Zeno Debuts World’s Smallest SRAM Technology at IEDM Conference

Zeno Debuts World’s Smallest SRAM Technology at IEDM Conference

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