1- /2-Transistor SRAM Technology Demonstrated at Standard FinFET Process Technology Sunnyvale, CA, December 5, 2018 – Zeno Semiconductor, a Silicon Catalyst Portfolio Company, demonstrated the scalability of its novel 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to FinFET technology node at the IEDM Conference. The results from 14nm and 16nm FinFET technology nodes from multiple foundries follow previous implementation of Bi-SRAM technol

Novel 1-Transistor SRAM Technology 5x Smaller and Lower Power than Conventional SRAM Demonstrated at 28nm Process Technology Sunnyvale, CA, December 10, 2015 – Zeno Semiconductor today announced its novel 1-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology at the IEDM Conference. Zeno’s 1-transistor Bi-SRAM uses a single transistor as the memory bitcell and is therefore 5x smaller than conventional SRAMs which use 6-transistor bitcells (6T-SRAM). When impl

As we are celebrating 50th anniversary of Moore's Law, we are excited to present the details of the 1T-SRAM memory technology at the IEDM 2015 conference in Washington, DC. Our 1T-SRAM memory technology provides a 5x smaller cell size compared to the conventional 6T-SRAM, promising to provide an alternative scaling method beyond Moore's Law. The paper is titled "A Novel Bi-stable 1-Transistor SRAM for High Density Embedded Application" and is a result of the collaborative wor