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1- /2-Transistor SRAM Technology Demonstrated at Standard FinFET Process Technology

Sunnyvale, CA, December 5, 2018 – Zeno Semiconductor, a Silicon Cat...

Zeno Demonstrates Scalability of World’s Smallest SRAM Bitcell Technology to FinFET Technology Node at IEDM Conference

December 5, 2018

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1-Transistor SRAM Cell Scales to FinFET Technology Node

December 6, 2018

Zeno’s 1-transistor Bi-SRAM uses a single transistor and is ~5x smaller than a conventional SRAM -- which use 6-transistor bitcells (6T-SRAM) -- at the same technology node.​

 

 

One way to look at a System-on-Chip (SoC) is the proportions of silicon area that are devoted to new logic, reused logic (from an earlier design), and embedded memory. According to Semico Research, in 1999, the area devoted to memory averaged out at 17%. By 2018, embedded memory has become pervasive -- designers demand more and more -- and the area devoted to memory has risen to 72%. Semico Research predicts that this will rise to 79% by 2021.

 

Of course, this doesn't mean that the amount of logic in new designs is falling -- on the contrary, the size, capacity, and performance of logic is increasing in leaps and bounds -- but the quantity of memory is increasing at a dramatically higher rate, especially in the case of the devices using in advanced technologies like artificial intelligence (AI), machine learning (ML), virtual reality (VR), and augmented reality (AR).

 

Conventional SRAMs use 6-transistor bitcells (6T-SRAM); by comparison, the folks at Zeno Semiconductor develop and license novel memory and logic technologies, including 2T-SRAM for high performance and 1T-SRAM for high density. The 2T technology is ~3X smaller than 6T at the same technology node, while the 1T technology is ~5X smaller (these numbers include all necessary peripheral circuitry, such as address decoders, read/write logic, etc.).

 

Read more on EE Web site.

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