top of page
Zeno 1-transistor Bi-SRAM (bi-stable, BiCMOS) provides a static memory cell with 5x smaller cell size. It is bi-stable, hence does not require refresh operation, and is compatible with CMOS logic process.
The Bi-SRAM memory schematic cross-section is shown. The bi-stable characteristics is obtained through the intrinsic, vertical, open-base bipolar transistors highlighted. The technology has been demonstrated at 28nm (presented at IEDM 2015) and 14/16nm (presented at IEDM 2018) technology nodes.
Memory Technology: Bi-SRAM
On-chip memory density continuously increases at a rapid pace. As shown in the Semico Research report, the area occupied by embedded memory is >50% of the total SoC area.
bottom of page