Shrinking SRAM expands on-chip memory with standard CMOS, FinFET
San Jose, Calif.-based startup Zeno Semiconductor is testing modifications and a smaller process node for the single-transistor 28nm SRAM chip it introduced in 2016, which could boost space for on-chip CPU memory by more than 2.5X, according to the co-founder and CEO of the company, Yuniarto Widjaja.
The Zeno-1 transistor is built on standard CMOS processes, has a bi-stable bipolar transistor built into its structure, which includes an N-well buried under a floating P-well on top of a P substrate.
The memory bitcell is genuinely static; it does not require a capacitor or other mechanism to maintain or refresh charge during operation, a capability it creates using the intrinsic bipolar transistor that are intrinsic to both CMOS and FinFET.
Because it uses one transistor rather than six, it is dramatically smaller than comparable unite, Widjaja said, which gives CPU makers the chance to expand on-chip memory without expanding the size of the die.
Read more on Semiconductor Engineering site.