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On-chip memory density continuously increases at a rapid pace.  As shown in the following chart, the area occupied by memory (which is currently dominated by 6-transistor or 8-transistor static random access memory SRAM) is already greater than that of logic in a typical SoC application.  There is clearly a significant demand for a smaller on-chip memory structure.


Zeno provides novel memory technologies that allow for significant reduction in memory cell size.  Zeno's 1-transistor SRAM is more than 80% smaller in size compared to the conventional 6-transistor or 8-transistor memory technology.  Zeno memory cell is also suitable for embedded memory applications as it is compatible with the existing CMOS processes.


As shown in the above diagram, Zeno's 1-transistor memory cell is a bi-stable memory cell, analogous to an SRAM cell.  This is in contrast to a dynamic random access memory (DRAM), which only has a single stable state, and thus requires periodic refresh operation.  Therefore, both states in a Zeno's memory cell are stable while power is applied to the memory cell.  

Currently, Zeno has more than 40 US and international patent applications, in which 23 of them have been granted.

Please email to contact@zenosemi.com for more information. 


News
December 10, 2012
Congratulations to Dr. Jin-Woo Han on receiving IEEE Early Career Award
September 4, 2012
Zeno Semiconductor, Inc. has been awarded NSF SBIR Phase II grant
March 6, 2012
Zeno has been granted the 10th US patent on its innovative memory technology
December 1, 2011
Dr. Stefan K. Lai, a pioneer in Flash memory, joins as member of Advisory Board
July 18, 2011
Dr. Serguei Okhonin, a co-founder of Innovative Silicon, has joined Zeno as a member of Advisory Board
January 2, 2011
Receives 2nd Phase I NSF SBIR Funding
May 15, 2010
First US patent granted

June 2, 2009
Completes first working prototype

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